CPLDs are well-known integrated circuits that may be programmed to perform various logic functions. Numerous types of memory elements may be used in CPLD architectures to provide programmability. One such memory element, known as a flash memory cell, is both electrically erasable and programmable. Program and erase are performed on a plurality of flash memory cells using either Fowler-Nordheim (F-N) Tunneling or hot electron injection for programming and F-N Tunneling for erase. Flash memories can also be In-System Programmable (ISP). An ISP device is a device that can be programmed, erased, and verified after it has been connected, such as by soldering, to the system printed circuit board. Some CPLDs don't have ISP capability and must be programmed externally (outside the system) by programming equipment.
ISP CPLDs typically have two test modes: external mode and ISP mode. External mode requires special test equipment that can externally supply the high-level voltages required to program, erase, and verify the device. In ISP mode, internal charge pumps generate the high-level voltages from the operating voltage, and no special equipment is required. Some CPLDs use programmable charge pumps to generate the voltages needed for programming, erasing, and margin verifying during ISP. Such programmable charge pumps are well known. Lee et al describe a number of illustrative programmable charge pump circuits in U.S. Pat. No. 5,661,685, entitled "Programmable Logic Device with Configurable Power Supply", and assigned to Xilinx, Inc., the assignee of the present invention. U.S. Pat. No. 5,661,685 is incorporated herein by reference.
Programmable charge pumps are designed to be adjustable so that voltage levels can be changed to compensate for process variations during fabrication, which can cause shifts in the output voltage of the charge pumps. Application of very accurate voltage levels during programming, erasing, and verifying operations is critical to the success of programming or erasing a cell. For example, to program a cell in one well-known type of CPLD, voltages are applied to the wordline (gate) of the cell as well as the cell's bitline (drain). During erase, a voltage is applied to the source side of the cell to induce tunneling of the electrons off of the floating gate. Because of the importance of these voltage levels during operation, it is critical that optimum voltage levels are set in the device. Using optimum voltage levels ensures reliability of the device and optimum programming and erase times for the user.
Process variations alter the CPLD internal voltage levels from batch to batch. Thus, CPLDs processed within a single fabrication batch may work well at specified voltage levels, while CPLDs made in other batches do not necessarily work at the same voltage levels. More specifically, CPLDs made in other fabrication batches may not work well at the initially specified voltages, and yield may be considerably lower.
Process variations may affect charge pump accuracy from batch to batch, as well as affecting optimum voltage levels for programming, erasing, and verifying the device. Therefore, there is a need for a method of determining optimum charge pump settings for a particular batch of CPLDs, and using these optimum settings for CPLDs within the batch to maximize yield.